Design-Reuse

Xilinx Pcie specification IP Listing

Rambus PCIe 3.0 Controller is a highly configurable PCIe 3.0 interface Soft IP designed for ASIC and FPGA implementations supporting endpoint, root port, switch, bridge and advanced features ...
Design-Reuse

Xilinx Ships FPGA Industry's Only Compliant Programmable x8 PCI Express IP Core

SAN JOSE, Calif. -- Feb. 7, 2006 -- Xilinx, Inc. (Nasdaq: XLNX - News) today announced immediate availability of its compliant x1, x4 and x8 lane LogiCORE(TM) PCI Express IP Core ("PCIe IP Core") ...
EDN

Programmable x8 PCIe IP core makes PCI-SIG Integrators List

San Jose, Calif.— Xilinx, Inc. announced immediate availability of its compliant x1, x4 and x8 lane LogiCORE PCI Express IP Core targeted for telecom, networking, storage and video applications. The ...
Business Wire

Enyx Premieres 25G TCP and UDP Offload Engines with Xilinx Virtex UltraScale+ 16nm FPGA on BittWare’s XUPP3R PCIe Board

SALT LAKE CITY--(BUSINESS WIRE)--SC16 Conference — Enyx is pleased to announce the 25G version of its enterprise-class TCP/IP, UDP/IP and MAC Intellectual Property ...
Electronic Design

IP Core Meets PCI Express

Poised for telecom, networking, storage, and video applications, the LogiCORE PCIe IP core is compliant with the PCI Express base specification v1.1. The core completed the rigorous Gold tests for ...