Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
Nature

High-Performance Sorting Algorithms and Architectures Using FPGA

Field-programmable gate arrays (FPGAs) offer a unique platform for the implementation of high-performance sorting algorithms by combining inherent parallelism with customisable hardware architectures.
Business Wire

Liquid-Markets Announces a Range of Intel FPGA-based Products for Financial Services and Beyond

ZUG, Switzerland--(BUSINESS WIRE)--Liquid-Markets GmbH (“LMS”) today announced a strategic collaboration with Intel Corporation to propel development of a range of Intel Agilex FPGA-based products to ...
EDN

How to accelerate algorithms by automatically generating FPGA coprocessors

Today's designers are constrained by space, power, and cost, and they simply cannot afford to implement embedded designs with gigahertz-class computers. Fortunately, in embedded systems, the greatest ...