EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
TechRepublic

Design of FPGA Based 32-Bit Floating Point Arithmetic Unit and Verification of Its VHDL Code Using MATLAB

Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources ...
Design-Reuse

Sundance and Dillon Marry Fastest FFT with Fastest Virtex-5 LXT FPGA

Sundance and Dillon Engineering Merge Signal Processing Expertise and FFT IP to Deliver Benchmark Performance for Embedded Defense, Industrial, Geophysical & Medical Systems London, UK and Edina, ...