EDN

Evaluate reference clocks for serial-data jitter specifications

Almost all high-speed SERDES designs require reference clocks that you must properly select to ensure that your links meet jitter requirements of high-speed serial-data communication standards.
EDN

LTC Design Note: Robust 10MHz reference clock input protection circuit and distributor for RF systems

RF instruments and wireless transceivers often feature an input for an external reference clock, such as the ubiquitous 10MHz reference input port found on RF instruments. Many of these same systems ...
New Electronics

Enhanced primary reference clock standards for precision time raises the performance bar for atomic standards

Microsemi has completed certification of its portfolio of Cesium clocks to be compliant with the new G.811.1 recommendation. This standard is known as ‘enhanced Primary Reference Clocks’ (ePRC) and is ...
New Electronics

Using WiLink 8 as a reference clock for the network time protocol

One of the challenges facing those developing networks featuring wirelessly connected devices is maintaining a common clock time. A popular way of doing this is by using Network Time Protocol (NTP), a ...
Electronic Design

Clocking Data Converters

What is the most critical performance characteristic for clock chips used with high-performance data converters? The clock signal’s phase noise (or jitter—the time-domain representation of phase noise ...