For testing complex chip designs it makes sense to combine the two most common test methodologies -logic built-in self-test (LBIST) and automatic test pattern generation (ATPG), writes Amer ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

This is just a general question. I know, obviously, that there are RS-232 "serial ports" and IEEE 1284/Centronix ports "parallel ports," and that these are "digital" connections. Then you have things ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, ...

Advanced ATPG products support simultaneous analysis of multiple fault models, leverage multi-threading and on-chip compression to improve quality and reduce turnaround time and costs of nanometer ICs ...

Test points for hybrid ATPG/LBIST applications make it easier to reach the ISO 26262 standard of 90% stuck-at coverage for in-system test. The remarkable growth in automotive IC design has prompted a ...

Two test strategies are used to test virtually all IC logic: automatic test pattern generation (ATPG) with test pattern compression and logic built-in self-test (BIST). This article will describe how ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...